1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a burst access mode enabling fast reading for use in a memory card or the like.
2. Description of Related Art
Recently an integration size of a semiconductor device has been increased by a progress of process technologies, thereby increasing an operation speed. Particularly it is remarkably increasing the operation speed of a CPU (central processing unit). According to increment of the operation speed of CPU, it is required to increase a readout operation speed of semiconductor memory.
Specifically music information or image information such as animation stored in a single semiconductor chip is reproduced by means of a speaker or by means of a display unit. If a read-out speed fluctuates during reading the music or image information, the reproduced music or image information becomes discontinuous, interfering with the user""s enjoyment.
Therefore, a high and constant speed operation is required for the readout processing of the music or image information.
In response to the request for a high-speed access to the semiconductor memory in the above, a burst mode is used for the operation of the semiconductor memory. In the burst mode, when a reference address is provided for the semiconductor memory, all of data corresponding to a page is previously latched. Subsequently, an internal circuit continuously generates addresses for burst mode, the latched data are readout in response to the addresses. That is, it is not necessary to read an address anew whenever data is read. Thus, a readout operation speed of semiconductor memory can be increased.
In other words, as shown in FIG. 5, 16-byte data of memory cells having byte 0 to byte 15 are read out during a latency period and subsequently 16-byte data of memory cells having byte 16 to byte 31 are read out while the data of the byte 0 to byte 15 are output. This readout operation is sequentially repeated.
In the burst mode, however, the semiconductor memory is provided with the next page address anew every readout operation of one page. Therefore, it is necessary to have time for decoding the next page address and reading page data from the memory cells by using a sense amplifier.
Furthermore, as shown in FIG. 6, when data is read from the middle of the 16 byte data, for example, from byte 15, only a readout period of a single byte data is allowed. However, the period is not sufficient to read the next page data (from byte 16 to byte 31) from memory cells, so that a continuous data output cannot be performed.
Therefore, in a method of latching a single-page data as described above, practically there is a limit to an improvement of an access time for a high-speed access. Accordingly a system with such a semiconductor memory cannot be improved in its processing speed.
To remove the above disadvantage, Japanese Kokai No. 9-106689 discloses an arrangment in which each bit line is connected to a sense amplifier and a latch so that a new address need not be inputted whenever a page is changed to the next one.
That is, data is read from all the bit lines all together and each data is stored in a latch. Thus, fast read/write page operation is performed without a new address, except for selecting a word line. Consequently, a system having such semiconductor memory does not need a page readout time for changing a page, thereby improving the speed of readout operation.
The above semiconductor memory, however, has to be equipped with sense amplifiers corresponding to all bit lines, and latches for storing data of these sense amplifiers. Although the speed of read-out operation increases, a chip size of such semiconductor memory is larger than that of a general semiconductor memory having the same capacity, since the sense amplifiers and the latches occupy a very large area of the chip area.
In addition, the semiconductor memory having the sense amplifiers corresponding to all bit lines has a very large power consumption in a data readout or other operations. If a portable information unit driven by a battery uses such semiconductor memory, the semiconductor memory reduces the operation time of the portable information unit.
Japanese Kokai No. 11-176185 discloses the semiconductor memory device including memory cell array divided into a plurality of blocks and a sense amplifiers shared between a plurality of columns in each of the blocks. The data of selected columns in the plurality of blocks is treated as a set of data.
According to such semiconductor memory device, after a first set of data is transferred from a sense amplifier to a shift register, a column address is incremented and the sense amplifier reads a second set of data. Then, the last data of the first set of data transferred to the shift register and the second set of data is transferred to the shift register. After the column address is incremented, the sense amplifier reads a third set of data.
This semiconductor memory device starts an output of data from the shift register after a predetermined random access time (for example, 1 xcexcsec). However, this semiconductor memory device is not provided with any means of detecting whether the second set of data is determined by the sense amplifier when all of the first set of data is output.
Therefore, if a random access time of an external circuit or an external unit is shorter than that of the semiconductor memory, the external circuit or the external unit reads out the second set of data from the shift register after outputting the first set of data, though all of the second set of data has not been determined yet. Accordingly, the external circuit and the external unit cannot receive accurate data.
In addition, after transferring the first set of data from the sense amplifier to the shift register, the column address is incremented, and the sense amplifier reads the second set of data. That is, the sense amplifier is always operating. Accordingly, the current always flows through the sense amplifier, thereby increasing the current consumption.
To resolve the above problems, a semiconductor memory device having a plurality of memory cell arrays divided into a plurality of blocks, each of sense amplifiers sharing a plurality of columns in each of the blocks, and two systems of latches for storing data from each of the sense amplifiers is considered.
In such semiconductor memory device, as shown in FIG. 7, during 16-byte data output, byte 0 to byte 15, stored in one latch, another 16-byte data, byte 16 to byte 31, is read out from memory cells and is stored in the other latch in response to a latch signal. In the timing chart shown in FIG. 7, when a chip select signal CE is at a High level, the semiconductor memory is available.
The semiconductor memory device sequentially repeats this reading and storing process for respective latches. The sense amplifier is assumed to be in an operating condition (signal SAEB is at a Low level) only for a period of reading data for latches.
The number of sense amplifiers can be decreased by performing the data output and the data storing alternately. Therefore, an access time improvement is achieved in the burst mode without any enlargement of a chip area and any increase of power consumption, since the sense amplifiers are driven only for reading data from the memory cells.
However, if the chip select signal CE changes to a Low level, all of the circuits in the memory are brought into an unavailable condition (standby condition), while the data outputting and the data storing are performed alternately. That is, the operation of the sense amplifier is interrupted and the latches which store next data cannot store accurate data.
In other words, as shown in FIG. 8, in the standby condition, the sense amplifier and a word line change from an active condition to an inactive condition. Thus, data read from the memory cells to the sense amplifier circuit vanish.
After that, even if the chip select signal CE changes to a High level and the semiconductor memory changes from the standby condition to the active condition, data cannot be read from the memory cell to the sense amplifier circuit, since a word line does not drop to a sufficiently low voltage level in a short time.
Consequently, the sense amplifier cannot accurately determine data of the memory cell and the latches cannot store accurate next data. After data from byte 0 to byte 15 is read out from one latch, data from byte 16 to byte 31 that is output from the other latch is not correct.
An object of the present invention is to provide a semiconductor memory device, which allows high and constant speed readout operation without enlargement of chip area.
Another object of the present invention is to provide a semiconductor memory device, which outputs data of memory cells correctly.
A semiconductor memory device according to the present invention includes a memory cell array having a plurality of memory cells; a plurality of word lines connected to the memory cells; a row decoder connected to the word lines so as to selectively enable one of the word lines; a plurality of digit lines coupled to the memory cells; a sense amplifier circuit having a plurality of sense amplifiers, each of the sense amplifiers being coupled to a respective one of the digit lines; a first latch circuit connected to the sense amplifier circuit so as to latch data of the digit lines; and a control circuit coupled to the row decoder and provided with a chip enable signal which is indicative of an operation mode of the semiconductor memory device so as to inactivate the row decoder when both the first latch circuit finishes latching the data of the digit lines and the chip enable signal is indicative of standby mode of the semiconductor memory device.
These and other objects of the present invention will be apparent to those of skill in the art from the appended claims when read in light of the following specification and accompanying figures.